Blog Review: Feb. 18
Agentic disruption; data center PUE; scaling AI; RTOS; dropping toast. The post Blog Review: Feb. 18 appeared first on Semiconductor Engineering.
Synopsys’ Raja Tabet anticipates deployment of an agentic AI workforce within the next 12 to 24 months that can take on different engineering personas, such as a digital implementation agent, a verification agent, or an analog agent, to run experiments in parallel, generate and triage tests, and propose fixes.
Cadence’s Reela Samuel dives into power usage effectiveness in data centers and why power density, rack layout, cooling topology, and containment strategy determine efficiency over a facility’s lifetime.
Siemens’ Miguel Cabezas Vega enlists simulation to probe the phenomenon of dropped toast landing butter-side down.
Keysight’s Armando Valim explains why scaling AI is a system-wide engineering exercise that requires treating infrastructure as a connected ecosystem spanning pre-silicon, wafer, chip, board, server, rack, data center, and edge.
Arm’s Zineb Labrut introduces Zephyr RTOS support through BayLibre for Armv9-A, including Scalable Vector Extension context management and unified Fixed Virtual Platform, to enable efficient, real-time edge AI deployments.
Ansys’ Wim Slagter looks at how emerging technologies, new architectures, and the rise of exascale computing are reshaping the future of engineering simulation.
The ESD Alliance’s Bob Smith chats with Synopsys’ Sutirtha Kabir about trends driving the need for collaboration between design, manufacturing, and OSATs.
Plus, catch up on the blogs featured in the latest Automotive, Security & Emerging Technologies, Test, Measurement & Analytics, and Low Power-High Performance newsletters:
Technology strategy advisor Geoff Tate digs into photonics and how it will replace copper for all interconnects in ~5 years, with TSMC potentially going from zero to #1.
Imagination Technologies’ Matthew Applegate digs into algorithms and why new applications are driving a growing preference for energy efficiency and throughput over strict precision.
Siemens EDA’s Pratyush Kamal and Todd Burkholder outline how the pace of innovation in advanced packaging is rewriting rules that IC and package teams have relied on for decades.
Rambus’ Berardino Carnevale warns that compromising a single weak chiplet or the interconnect can be sufficient to threaten the entire device platform.
Synaptics’ Neeta Shenoy explains how protocol management, real-time decision-making, on-device AI, and sensor fusion drive device intelligence.
Keysight’s Scott Register contends that cybersecurity has moved from a contractual footnote to a deciding factor for who gets to compete, especially for the defense/industrial base.
Synopsys’ Dana Neustadter and Vincent van der Leest show the high-level architecture and system-level integration of a dedicated security framework for point-to-point accelerator links.
Cadence’s Tanushri Shah looks at neuromorphic chips for processing temporal sensor data at the source in real-time, with a fully analog pipeline that only sends information to an MCU when necessary.
PDF Solutions’ Christophe Begue outlines a faster way to find yield-killing defects that are deeply buried within complex structures.
Siemens EDA’s Peter Orlando looks at system-level test and finds that patterns created using advanced fault models provide higher test coverage, improved defect detection, and higher-yielding silicon.
Rambus’ Raj Uppala shows why matching memory technology to the inference workload phase is necessary to achieve the lowest cost per served token.
Siemens EDA’s Nicolae Tusinschi discusses ways to manage complexity without compromising mathematical rigor.
Cadence’s Vinod Khera digs into data center power, cooling, and sustainability, noting that as rack densities rise and cooling architectures diversify, design mistakes are costly.
Synopsys’ Andrew Appleby explains how to unlock new levels of power and cost efficiency through innovation across process, design, and architecture.
Arm’s Bolt Liu delves into non-uniform memory access and how NUMA-aware optimizations can deliver up to 55% faster text generation.
The post Blog Review: Feb. 18 appeared first on Semiconductor Engineering.
Cadence’s Reela Samuel dives into power usage effectiveness in data centers and why power density, rack layout, cooling topology, and containment strategy determine efficiency over a facility’s lifetime.
Siemens’ Miguel Cabezas Vega enlists simulation to probe the phenomenon of dropped toast landing butter-side down.
Keysight’s Armando Valim explains why scaling AI is a system-wide engineering exercise that requires treating infrastructure as a connected ecosystem spanning pre-silicon, wafer, chip, board, server, rack, data center, and edge.
Arm’s Zineb Labrut introduces Zephyr RTOS support through BayLibre for Armv9-A, including Scalable Vector Extension context management and unified Fixed Virtual Platform, to enable efficient, real-time edge AI deployments.
Ansys’ Wim Slagter looks at how emerging technologies, new architectures, and the rise of exascale computing are reshaping the future of engineering simulation.
The ESD Alliance’s Bob Smith chats with Synopsys’ Sutirtha Kabir about trends driving the need for collaboration between design, manufacturing, and OSATs.
Plus, catch up on the blogs featured in the latest Automotive, Security & Emerging Technologies, Test, Measurement & Analytics, and Low Power-High Performance newsletters:
Technology strategy advisor Geoff Tate digs into photonics and how it will replace copper for all interconnects in ~5 years, with TSMC potentially going from zero to #1.
Imagination Technologies’ Matthew Applegate digs into algorithms and why new applications are driving a growing preference for energy efficiency and throughput over strict precision.
Siemens EDA’s Pratyush Kamal and Todd Burkholder outline how the pace of innovation in advanced packaging is rewriting rules that IC and package teams have relied on for decades.
Rambus’ Berardino Carnevale warns that compromising a single weak chiplet or the interconnect can be sufficient to threaten the entire device platform.
Synaptics’ Neeta Shenoy explains how protocol management, real-time decision-making, on-device AI, and sensor fusion drive device intelligence.
Keysight’s Scott Register contends that cybersecurity has moved from a contractual footnote to a deciding factor for who gets to compete, especially for the defense/industrial base.
Synopsys’ Dana Neustadter and Vincent van der Leest show the high-level architecture and system-level integration of a dedicated security framework for point-to-point accelerator links.
Cadence’s Tanushri Shah looks at neuromorphic chips for processing temporal sensor data at the source in real-time, with a fully analog pipeline that only sends information to an MCU when necessary.
PDF Solutions’ Christophe Begue outlines a faster way to find yield-killing defects that are deeply buried within complex structures.
Siemens EDA’s Peter Orlando looks at system-level test and finds that patterns created using advanced fault models provide higher test coverage, improved defect detection, and higher-yielding silicon.
Rambus’ Raj Uppala shows why matching memory technology to the inference workload phase is necessary to achieve the lowest cost per served token.
Siemens EDA’s Nicolae Tusinschi discusses ways to manage complexity without compromising mathematical rigor.
Cadence’s Vinod Khera digs into data center power, cooling, and sustainability, noting that as rack densities rise and cooling architectures diversify, design mistakes are costly.
Synopsys’ Andrew Appleby explains how to unlock new levels of power and cost efficiency through innovation across process, design, and architecture.
Arm’s Bolt Liu delves into non-uniform memory access and how NUMA-aware optimizations can deliver up to 55% faster text generation.
The post Blog Review: Feb. 18 appeared first on Semiconductor Engineering.